1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which comprises a delay circuit which consists of a plurality of series-connected inverters.
2. Description of the Prior Art
FIG. 1 is a circuitry diagram showing a structure of a phase comparison device, i.e., a 1-chip semiconductor integrated circuit which comprises a delay circuit which consists of a plurality of series-connected inverters.
As shown in. FIG. 1, the phase comparison device is comprised of a phase comparison part 30 and an inverter circuit block 40. The inverter circuit block 40 is a delay circuit which consists of a plurality of (even number of) series-connected CMOS inverters (not shown), and connected to both a power source voltage V.sub.DD and a ground level. An output signal S3 from a NAND gate G3 is delayed by a time TA in the inverter circuit block 40 and outputted from the same as a delayed signal S3' which will be thereafter transmitted to a node N1 of the phase comparison part 30.
The phase comparison part 30 is formed by nine NAND gates G1 to G9. The NAND gates G1 and G2 are each a three-input NAND gate, the NAND gate G3 is a four-input NAND gate, and the NAND gates G4 to G9 are each a two-input NAND gate. The NAND gates G1 to G9 each have a CMOS structure.
In FIG. 1, indicated at reference character I1 is a reference signal and indicated at reference character I2 is a signal-to-be-controlled. The reference signal I1 is given to the NAND gate G4 as one input thereto. An output from the NAND gate G4 is given to the NAND gates G1 and G3 as a first input thereto and also to the NAND gate G5 as one input thereto. An output from the NAND gate G5 is given to the NAND gates G1 and G3 as a second input thereto and also to the NAND gate G6 as one input. An output from the NAND gate G6 is returned to the NAND gate G5 as the other input thereto.
The signal-to-be-controlled I2 is fed to the NAND gate G9 as one input thereto. An output from the NAND gate G9 is given to the NAND gate G2 as a first input, to the NAND gate G3 as a third input and to the NAND gate G8 as one input. An output from the NAND gate G8 is given to the NAND gate G2 as a second input, to the NAND gate G3 as a fourth input and to the NAND gate G7 as one input. An output from the NAND gate G7 is returned to the NAND gate G8 as the other input thereto.
The output signal S3 from the NAND gate G3 is a signal which is to be transmitted to the inverter circuit block 40. Delayed by a predetermined time in the inverter circuit block 40, the signal S3 is outputted from the inverter circuit block 40 as the delayed signal S3' which is to be given to the node N1. The delayed signal S3' is then routed from the node N1 to the NAND gates G1 and G2 as a third input thereto and to the NAND gates G6 and G7 as the other input thereto.
Signals Q1 and Q2 available at output parts of the NAND gates G1 and G2 are phase compared output signals.
Of the NAND gates G1 to G9 thus connected to each other, the NAND gates G1 and G4 form a first flip-flop, the NAND gates G5 and G6 form a second flip-flop, the NAND gates G2 and G9 form a third flip-flop, and the NAND gates G7 and G8 form a fourth flip-flop.
If the signal-to-be-controlled I2 leads the reference signal I1, the phase compared output signal Q2 from the phase comparison device has an L level pulse whose pulse width is proportional to the phase difference between the signals I1 and I2. If the signal-to-be-controlled I2 lags the reference signal I1, on the other hand, it is the phase compared output signal Q1 from the phase comparison device that has an L level pulse whose pulse width is proportional to the phase difference between the signals I1 and 12.
FIG. 2 is a waveform diagram illustrating phase comparison (FIG. 1) performed by the phase comparison part 30. As shown in FIG. 2, if the signal-to-be-controlled I2 lags the reference signal I1 by a time TG, the phase compared output signal Q1 has an L level pulse of a pulse width (TG+TA) while the phase compared output signal Q2 has an L level pulse of a pulse width TA.
The pulse width TA is a delay time which is implemented by the inverter circuit block 40. The reason for additionally implementing the pulse width TA in the L level pulses of the phase compared output signals Q1 and Q2 of the phase comparison part 30 is to ensure that a next circuit connected to this phase comparison device, such as a charging pump and an integrating circuit, responds quickly and operates normally in response to the phase compared output signals Q1 and Q2. If the pulse width TA is shorter or longer than a predetermined width, the next circuit will not operate precisely as it is desired to do. Hence, the pulse width TA to be implemented by the inverter circuit block 40 must have a fixed constant width.
As hereinabove described, the conventional phase comparison device requires that the inverter circuit block 40 delays the signal S3, which is outputted from the phase comparison part 30, by the delay time TA. As a result, the phase compared output signals Q1 and Q2 as desired are generated.
However, the conventional phase comparison device has a limited success in this regard. If a plurality of power source voltages are used due to specifications regarding a power source of the phase comparison part, the delay time TA implemented by the inverter circuit block 40 changes with different power source voltages.
In other words, the conventional phase comparison device can be used with only one power source voltage, or otherwise, the delay time TA as precisely desired will not be obtainable.